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Espressif Systems /ESP32-C3 /SENSITIVE /CORE_X_IRAM0_PMS_CONSTRAIN_1

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Interpret as CORE_X_IRAM0_PMS_CONSTRAIN_1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS

Description

SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG

Fields

CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0

core_x_iram0_pms_constrain_sram_world_1_pms_0
CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1

core_x_iram0_pms_constrain_sram_world_1_pms_1
CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2

core_x_iram0_pms_constrain_sram_world_1_pms_2
CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3

core_x_iram0_pms_constrain_sram_world_1_pms_3
CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0

core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0
CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS

core_x_iram0_pms_constrain_rom_world_1_pms

Links

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Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data